View LM3489QMMNOPB_9067313.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 hysteretic pfet buck controller with enable pin check for samples: lm3489 , lm3489-q1 1 features description the lm3489 is a high efficiency pfet switching 2 ? easy to use control methodology regulator controller that can be used to quickly and ? no control loop compensation required easily develop a small, cost effective, switching buck ? wide 4.5v to 35v input range regulator for a wide range of applications. the hysteretic control architecture provides for simple ? 1.239v to v in adjustable output range design without any control loop stability concerns ? high efficiency 93% using a wide variety of external components. the ? 1.3% ( 2% over temp) internal reference pfet architecture also allows for low component count as well as ultra-low dropout, 100% duty cycle ? 100% duty cycle operation operation. another benefit is high efficiency operation ? maximum operation frequency > 1mhz at light loads without an increase in output ripple. a ? current limit protection dedicated enable pin provides a shutdown mode drawing only 7 a. leaving the enable pin ? dedicated enable pin (on if unconnected) unconnected defaults to on. ? shutdown mode draws only 7 a supply current current limit protection can be implemented by measuring the voltage across the pfet ? s r ds(on) , ? vssop-8 thus eliminating the need for a sense resistor. a ? lm3489 is aec-q100 grade 1 qualified sense resistor may be used to improve current limit accuracy if desired. the cycle-by-cycle current limit applications can be adjusted with a single resistor, ensuring safe operation over a range of output currents. ? set-top box ? dsl or cable modem ? pc/ia ? auto pc ? tft monitor ? battery powered portable applications ? distributed power systems ? always on power ? high power led driver ? automotive typical application circuit 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. isense adj vin pgate fb en lm3489 gnd pgnd 1 2 3 4 5 6 7 8 + + q1 v in v out c in1 c out d1 l r adj r is c adj r1 r2 c ff c in2
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com connection diagram figure 1. top view 8-lead plastic vssop-8 package number (dgk) pin descriptions pin name description no. 1 isense the current sense input pin. this pin should be connected to the pfet drain terminal directly or through a series resistor up to 600 ohm for 28v > vin > 35v. 2 gnd signal ground. 3 en enable pin. connect en pin to ground to shutdown the part or float to enable operation (internally pulled high). this pin can also be used to perform uvlo function. 4 fb the feedback input. connect the fb to a resistor voltage divider between the output and gnd for an adjustable output voltage. 5 adj current limit threshold adjustment. connected to an internal 5.5 a current source. a resistor is connected between this pin and vin. the voltage across this resistor is compared with the isense pin voltage to determine if an over-current condition has occurred. 6 pgnd power ground. 7 pgate gate drive output for the external pfet. pgate swings between vin and vin-5v. 8 vin power supply input pin. 2 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1 isense gnd pgnd vin pgate adj fb en 1 2 3 4 5 6 7 8
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) vin voltage ? 0.3v to 36v pgate voltage ? 0.3v to 36v fb voltage ? 0.3v to 5v ? 1.0v to 36v isense voltage -1v ( < 100ns) adj voltage ? 0.3v to 36v en voltage (2) ? 0.3v to 6v maximum junction temperature 150 c power dissipation, t a = 25 c (3) 417mw esd susceptibility human body model (4) 2kv lead temperature vapor phase (60 sec.) 215 c infrared (15 sec.) 220 c storage temperature ? 65 c to 150 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. for specifications and test conditions, see the electrical characteristics. (2) this pin is internally pulled high and clamped at 8v typical. the absolute maximum and operating maximum rating specifies the input level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin. (3) the maximum allowable power dissipation is a function of the maximum junction temperature, t j_max , the junction-to-ambient thermal resistance, ja = 240 c/w, and the ambient temperature, t a . the maximum allowable power dissipation at any ambient temperature is calculated using: p d_max = (t j_max - t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature. (4) the human body model is a 100 pf capacitor discharged through a 1.5k resistor into each pin. the machine model is a 200pf capacitor discharged directly into each pin. mil-std-883 3015.7 operating ratings (1) supply voltage range (v in ) 4.5v to 35v en voltage (maximum) (2) 5.5v operating junction temperature (t j ) ? 40 c to +125 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. for specifications and test conditions, see the electrical characteristics. (2) this pin is internally pulled high and clamped at 8v typical. the absolute maximum and operating maximum rating specifies the input level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: lm3489 lm3489-q1
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com electrical characteristics (1) (2) specifications in standard type face are for t j = 25 c, and in bold type face apply over the full operating temperature range (t j = ? 40 c to +125 c). unless otherwise specified, v in = 12v, v isns = v in ? 1v, and v adj = v in ? 1.1v. datasheet min/max specification limits are specified by design, test, or statistical analysis. symbol parameter test conditions min typ max unit i shdn shutdown input supply current en = 0v 7 15 a v en enable threshold voltage enable rising 1.15 1.5 1.85 v v en_hyst enable threshold hysteresis 130 mv i q quiescent current at ground pin fb = 1.5v (not switching) 280 400 a v fb feedback voltage 1.223 1.239 1.255 v (3) 1.214 1.264 v hyst comparator hysteresis 10 15 mv 14 20 v cl_offset current limit comparator offset v fb = 1.0v -20 0 +20 mv i cl_adj current limit adj current source v fb = 1.5v 3.0 5.5 7.0 a t cl current limit one shot off time v adj = 11.5v 6 9 14 s v isns = 11.0v v fb = 1.0v r pgate driver resistance source 5.5 ? i source = 100ma sink 8.5 i sink = 100ma i pgate driver output current source 0.44 a v in = 7v, pgate = 3.5v sink 0.1 vin = 7v, pgate = 3.5v i fb (4) fb pin bias current v fb = 1.0v 300 750 na t onmin_nor minimum on time in normal v isns = v adj + 0.1v 100 ns operation c load on out = 1000pf (5) t onmin_cl minimum on time in current limit v isns = v adj - 0.1v 200 ns v fb = 1.0v c load on out = 1000pf (5) %v fb / v in feedback voltage line regulation 4.5 v in 35v 0.01 %/v (1) all limits are specified at room temperature (standard type face) and at temperature extremes (bold type face) . all room temperature limits are 100% tested. all limits at temperature extremes are specified via correlation using standard statistical quality control (sqc) methods. all limits are used to calculate average outgoing quality level (aoql). (2) typical numbers are at 25 c and represent the most likely norm. (3) the v fb is the trip voltage at the fb pin when pgate switches from high to low. (4) bias current flows out from the fb pin. (5) a 1000pf capacitor is connected between v in and pgate. 4 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 typical performance characteristics all curves taken at vin = 12v with configuration in design information . t j = 25 c, unless otherwise specified. quiescent current vs input voltage shutdown current vs input voltage figure 2. figure 3. feedback voltage vs temperature feedback voltage hysteresis vs input voltage figure 4. figure 5. feedback voltage hysteresis vs temperature current limit adj current vs temperature figure 6. figure 7. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: lm3489 lm3489-q1 -40 -20 0 20 40 60 80 100 140 junction temperature (c) 120 2 6 10 14 18 v hyst (mv) i out = 0 v in = 12v -40 -20 0 20 40 60 80 100 140 junction temperature (c) 120 4.5 5 5.5 6 6.5 i cl_adj ( p a) v fb = 1.5v 4.5v 18v 35v 0 10 20 30 40 2 6 10 14 16 v hyst (mv) v in (v) i out = 0 t j = 25c 1.214 1.224 1.234 1.244 1.254 1.264 -40 -20 0 20 40 60 80 100 140 junction temperature (c) v fb (v) 120 i out = 200 ma 18v 35v 12v 4.5v 0 10 20 30 40 0 3 6 9 12 15 i in ( p a) v in (v) v fb = 1.5v, v en = 5.5v -40c 25c 125c 0 10 20 30 40 0 100 200 300 400 500 i in ( p a ) v in (v) v fb = 1.5v, v en = 5.5v -40c 25c 125c
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com typical performance characteristics (continued) all curves taken at vin = 12v with configuration in design information . t j = 25 c, unless otherwise specified. current limit one shot off time vs temperature v in - v pgate vs v in figure 8. figure 9. minimum on time vs temperature (normal operation) minimum on time vs temperature (current limit) figure 10. figure 11. operating on time vs load current operating frequency vs input voltage figure 12. figure 13. 6 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1 0 40 0 100 200 300 400 500 600 operating frequency (khz) v in (v) 10 20 30 l = 10 p h l = 15 p h l = 22 p h v out = 3.3v i out = 500 ma c ff = 100 pf -40 -10 20 50 80 110 140 junction temperature, t j (c) 40 60 80 100 120 140 160 t onmin_nor (ns) v in = 4.5v v in = 24v v in = 12v -40 -10 20 50 80 110 140 junction temperature, t j ( o c) 100 150 200 250 300 t onmin_cl (ns) v in = 12v v in = 4.5v v in = 24v -40 -10 20 50 80 110 140 junction temperature, t j (c) 8 8.5 9 9.5 10 t cl ( p s) v in = 12v v in = 4.5v v in = 24v v in = 35v 0 40 3 3.5 4 4.5 5 5.5 6 v in -v pgate (v) v in (v) 10 20 30 -40c 25c 125c 0 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 operating on time ( p s) load current (a) v in = 12v v in = 6v v in = 24v
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 typical performance characteristics (continued) all curves taken at vin = 12v with configuration in design information . t j = 25 c, unless otherwise specified. efficiency vs load current v out regulation vs load current (v out = 3.3v, l = 22 h) (v out = 3.3v, l = 22 h) figure 14. figure 15. efficiency vs load current (v out = 5v, l = 22 h) v out regulation vs load current (v out = 5v, l = 22 h) figure 16. figure 17. continuous mode operation power up (no load, c adj = 1nf) (v in = 12v, v out = 3.3 v, i out = 500ma) figure 18. figure 19. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: lm3489 lm3489-q1 v out ripple (50 mvac/div) switch node voltage, v d1 (10v/div) i l (1a/div) time (2 p s/div) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 output current (a) 40 50 60 70 80 90 100 efficiency (%) l = 22 p h r1 = 60.7k r2 = 20k v in = 24v v in = 12v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 output current (a) -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 ' v out (%) v in = 24v v in = 12v l = 22 p h r1 = 60.7k r2 = 20k 0.0 0.2 0.4 0.6 0.8 1.0 1.2 output current (a) 40 50 60 70 80 90 100 efficiency (%) v in = 4.5v v in = 24v v in = 12v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 output current (a) -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 ' v out (%) v in = 4.5v v in = 24v v in = 12v
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com typical performance characteristics (continued) all curves taken at vin = 12v with configuration in design information . t j = 25 c, unless otherwise specified. discontinuous mode operation load transient (v in = 12v, v out =3.3 v, i out = 50ma) (v out = 3.3 v, 50 ma - 500 ma load) figure 20. figure 21. enable transient shutdown transient (v out = 3.3 v, 500 ma loaded) (v out = 3.3 v, 500 ma loaded) figure 22. figure 23. 8 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1 v out ripple (20 mvac/div) switch node voltage, v d1 (10v/div) i l (500 ma/div) time (4 p s/div)
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 simplified functional block diagram functional description overview the lm3489 is a buck (step-down) dc-dc controller that uses a hysteretic control scheme. the control comparator is designed with approximately 10mv of hysteresis. in response to the voltage at the fb pin, the gate drive (pgate pin) turns the external pfet on or off. when the inductor current is too high, the current limit protection circuit engages and turns the pfet off for approximately 9 s. hysteretic control does not require an internal oscillator. switching frequency depends on the external components and operating conditions. the operating frequency reduces at light loads resulting in excellent efficiency compared to other architectures. the output voltage can be programmed by two external resistors. the output can be set in a wide range from 1.239v (typical) to v in . hysteretic control circuit when the fb input to the control comparator falls below the reference voltage (1.239v), the output of the comparator switches to a low state. this results in the driver output, pgate, pulling the gate of the pfet low and turning on the pfet. with the pfet on, the input supply charges c out and supplies current to the load via the series path through the pfet and the inductor. current through the inductor ramps up linearly and the output voltage increases. as the fb voltage reaches the upper threshold, which is the internal reference voltage plus 10mv, the output of the comparator changes from low to high, and the pgate responds by turning the pfet off. as the pfet turns off, the inductor voltage reverses, the catch diode turns on, and the current through the inductor ramps down. then, as the output voltage reaches the internal reference voltage again, the next cycle starts. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: lm3489 lm3489-q1
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com the lm3489 operates in discontinuous conduction mode at light load current or continuous conduction mode at heavy load current. in discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. the next cycle starts when the fb voltage reaches the reference voltage. until then, the inductor current remains zero and the output capacitor supplies the load. the operating frequency is lower and switching losses reduced. in continuous conduction mode, current always flows through the inductor and never ramps down to zero. the output voltage (v out ) can be programmed by 2 external resistors. it can be calculated as follows: v out = 1.239 x (r1 + r2) / r2 (1) figure 24. hysteretic window the minimum output voltage ripple (v out_pp ) can be calculated in the same way. v out_pp = v hyst (r1 + r2) / r2 (2) for example, with v out set to 3.3v, v out_pp is 26.6mv v out_pp = 0.01 x (33k + 20k) / 20k = 0.0266v (3) operating frequency (f) is determined by knowing the input voltage, output voltage, inductor, v hyst , esr (equivalent series resistance) of output capacitor, and the delay. it can be approximately calculated using the formula: (4) where: : (r1 + r2) / r2 delay: it includes the lm3489 propagation delay time and the pfet delay time. the propagation delay is 90ns typically (see figure 25 ). 10 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 figure 25. propagation delay the operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor (cff). cff is connected in parallel with the high side feedback resistor, r1. the location of this capacitor is similar to where a phase lead capacitor would be located in a pwm control scheme. however it's effect on hysteretic operation is much different. cff effectively shorts out r1 at the switching frequency and applies the full output ripple to the fb pin without dividing by the r2/r1 ratio. the end result is a reduction in output ripple and an increase in operating frequency. when adding cff, calculate the formula above with = 1. the value of cff depend on the desired operating frequency and the value of r2. a good starting point is 470pf ceramic at 100khz decreasing linearly with increased operating frequency. also note that as the output voltage is programmed below 2.5v, the effect of cff will decrease significantly. current limit operation the lm3489 has a cycle-by-cycle current limit. current limit is sensed across the v ds of the pfet or across an additional sense resistor. when current limit is activated, the lm3489 turns off the external pfet for a period of 9 s(typical). the current limit is adjusted by an external resistor, r adj . the current limit circuit is composed of the isense comparator and the one-shot pulse generator. the positive input of the isense comparator is the adj pin. an internal 5.5 a current sink creates a voltage across the external r adj resistor. this voltage is compared to the voltage across the pfet or sense resistor. the adj voltage can be calculated as follows: v adj = v in ? (r adj x 3.0 a) (5) where 3.0 a is the minimum i cl-adj value. the negative input of the isense comparator is the isense pin that should be connected to the drain of the external pfet. the inductor current is determined by sensing the v ds . it can be calculated as follows. v isense = v in ? (r dson x i ind_peak ) = v in ? v ds (6) figure 26. current sensing by v ds copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: lm3489 lm3489-q1 input voltage - output voltage (v) propogation delay (ns) 0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 l=10 p h l=4.7 p h l=22 p h
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com the current limit is activated when the voltage at the adj pin exceeds the voltage at the i sense pin. the isense comparator triggers the 9 s one shot pulse generator forcing the driver to turn the pfet off. the driver turns the pfet back on after 9 s. if the current has not reduced below the set threshold, the cycle will repeat continuously. a filter capacitor, c adj , should be placed as shown in figure 26 . c adj filters unwanted noise so that the isense comparator will not be accidentally triggered. a value of 100pf to 1nf is recommended in most applications. higher values can be used to create a soft-start function (see start up section). the current limit comparator has approximately 100ns of blanking time. this ensures that the pfet is fully on when the current is sensed. however, under extreme conditions such as cold temperature, some pfets may not fully turn on within the blanking time. in this case, the current limit threshold must be increased. if the current limit function is used, the on time must be greater than 100ns. under low duty cycle operation, the maximum operating frequency will be limited by this minimum on time. during current limit operation, the output voltage will drop significantly as will operating frequency. as the load current is reduced, the output will return to the programmed voltage. however, there is a current limit fold back phenomenon inherent in this current limit architecture. see figure 27 . figure 27. current limit fold back phenomenon at high input voltages ( > 28v) increased undershoot at the switch node can cause an increase in the current limit threshold. to avoid this problem, a low vf schottky catch diode must be used (see catch diode selection). additionally, a resistor can be placed between the isense pin and the switch node. any value in the range of 220 ? to 600 ? is recommended. start up the current limit circuit is active during start-up. during start-up the pfet will stay on until either the current limit or the feedback comparator is tripped if the current limit comparator is tripped first then the fold back characteristic should be taken into account. start- up into full load may require a higher current limit set point or the load must be applied after start-up. one problem with selecting a higher current limit is inrush current during start-up. increasing the capacitance (c adj ) in parallel with r adj results in a soft-start characteristic. c adj and r adj create an rc time constant forcing current limit to activate at a lower current. the output voltage will ramp more slowly when using this technique. there is example start-up plot for c adj equal to 1nf in the typical performance characteristics. lower values for c adj will have little to no effect on soft-start. external sense resistor the v ds of a pfet will tend to vary significantly over temperature. this will result an equivalent variation in current limit. to improve current limit accuracy an external sense resistor can be connected from v in to the source of the pfet, as shown in figure 28 . the current sense resistor, r cs should have value comparable with r dson of the pfet used, typically in the range of 50m ? to 200 m ? . the equation in current limit operation can be used by replacing the r dson with r cs . 12 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 figure 28. current sensing by external resistor pgate when switching, the pgate pin swings from vin (off) to some voltage below vin (on). how far the pgate will swing depends on several factors including the capacitance, on time, and input voltage. pgate voltage swing will increase with decreasing gate capacitance. although pgate voltage will typically be around vin-5v, with very small gate capacitances, this value can increase to a typical maximum of vin-8.3v. additionally, pgate swing voltage will increase as on time increases. during long on times, such as when operating at 100% duty cycle, the pgate voltage will eventually fall to its maximum voltage of vin-8.3v (typical) regardless of the pfet gate capacitance. the pgate voltage will not fall below 0.4v (typical). therefore, when the input voltage falls below approximately 9v, the pgate swing voltage range will be reduced. at an input voltage of 7v, for instance, pgate will swing from 7v to a minimum of 0.4v. device enable, shutdown the lm3489 can be remotely shutdown by forcing the enable pin to ground. with en pin grounded, the internal blocks other than the enable logic are de-activated and the shutdown current of the device will be lowered to only 7 a (typical). releasing the en pin allows for normal operation to resume. the en pin is internally pulled high with the voltage clamped at 8v typical. for normal operation this pin should be left open. in case an external voltage source is applied to this pin for enable control, the applied voltage should not exceed the maximum operating voltage level specified in this datasheet, i.e. 5.5v. adjustable uvlo the under-voltage-lockout function can be implemented as shown in figure 29 . by incorporating the feature of the internal enable threshold, the lockout level can be programmed through an external potential divider formed with r3 and r4. the input voltage information is detected and compared with the enable threshold and the device operation will be inhibited when v in drops below the preset uvlo level. the uvlo and hysteresis voltage can be calculated as follows: (7) (8) where v en is the enable rising threshold voltage and v en_hyst is the enable threshold hysteresis. copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: lm3489 lm3489-q1 v in(uvlo_hyst) = v en_hyst x 1+ r4 r3 v in(uvlo) = v en 1 + r4 r3
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com figure 29. adjustable uvlo design information hysteretic control is a simple control scheme. however the operating frequency and other performance characteristics highly depend on external conditions and components. if either the inductance, output capacitance, esr, v in , or cff is changed, there will be a change in the operating frequency and output ripple. the best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and c out esr. inductor selection (l) the important parameters for the inductor are the inductance and the current rating. the lm3489 operates over a wide frequency range and can use a wide range of inductance values. a rule of thumb is to use the equations used for simple switchers ? . the equation for inductor ripple ( i) as a function of output current (i out ) is: for i out < 2.0amps i i out x i out ? 0.366726 for i out > 2.0amps i i out x 0.3 the inductance can be calculated based upon the desired operating frequency where: (9) and (10) where d is the duty cycle, v d is the diode forward voltage, and v ds is the voltage drop across the pfet. the inductor should be rated to the following: (11) the inductance value and the resulting ripple is one of the key parameters controlling operating frequency. the second is the inductor esr that contribute to the steady state power loss due to current flowing through the inductor. 14 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1 i pk = i out + ' i 2 x 1.1 i pk = i out + ' i 2 x 1.1 v in - v ds - v out l = ' i x d f isense adj vin pgate fb en lm3489 gnd pgnd 1 2 3 4 5 6 7 8 v in v en r3 r4
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 output capacitor selection (c out ) the esr of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. however, the v hyst sets the first order value of this ripple. as esr is increased with a given inductance, operating frequency increases as well. if esr is reduced then the operating frequency reduces. the use of ceramic capacitors has become a common desire of many power supply designers. however, ceramic capacitors have a very low esr resulting in a 90 phase shift of the output voltage ripple. this results in low operating frequency and increased output ripple. to fix this problem a low value resistor should be added in series with the ceramic output capacitor. although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. other types capacitor, such as sanyo pos cap and os-con, panasonic sp cap, and nichicon "na" series, are also recommended and may be used without additional series resistance. for all practical purposes, any type of output capacitor may be used with proper circuit verification. input capacitor selection (c in ) a bypass capacitor is required between the input source and ground. it must be located near the source pin of the external pfet. the input capacitor prevents large voltage transients at the input and provides the instantaneous current when the pfet turns on. the important parameters for the input capacitor are the voltage rating and the rms current rating. follow the manufacturer's recommended voltage derating. for high input voltage applications, low esr electrolytic, nichicon "ud" series or the panasonic "fk" series are available. the rms current in the input capacitor can be calculated as follows: (12) the input capacitor power dissipation can be calculated as follows. p d(cin) = i rms_cin 2 x esr cin (13) the input capacitor must be able to handle the rms current and the dissipation. several input capacitors may be connected in parallel to handle large rms currents. in some cases it may be much cheaper to use multiple electrolytic capacitors than a single low esr, high performance capacitor such as os-con or tantalum. the capacitance value should be selected such that the ripple voltage created by the switch current pulses is less than 10% of the total dc voltage across the capacitor. for high vin conditions ( > 28v), the fast switching, high swing of the internal gate drive introduces unwanted disturbance to the vin rail and the current limit function can be affected. in order to eliminate this potential problem, a high quality ceramic capacitor of 0.1 f is recommended to filter out the internal disturbance at the vin pin. this capacitor should be placed right next to the vin pin for best performance. programming the current limit (r adj ) the current limit is determined by connecting a resistor (r adj ) between input voltage and the adj pin, pin 5. (14) where: r dson : drain-source on resistance of the external pfet i cl_adj : 3.0 a minimum i ind_peak = i load + i ripple /2 using the minimum value for i cl_adj (3.0 a) ensures that the current limit threshold will be set higher than the peak inductor current. the r adj value must be selected to ensure that the voltage at the adj pin does not fall below 3.5v. with this in mind, r adj_max = (v in -3.5)/7 a. if a larger r adj value is needed to set the desired current limit, either use a pfet with a lower r dson , or use a current sense resistor as shown in figure 28 . copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: lm3489 lm3489-q1 r dson r adj = i ind_peak x i cl_adj v out (v in v out ) i rms_cin = i out x v in
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com the current limit function can be disabled by connecting the adj pin to ground and isense to vin. catch diode selection (d1) the important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. the average current through the diode can be calculated as following. i d_ave = i out x (1 ? d) (15) the off state voltage across the catch diode is approximately equal to the input voltage. the peak reverse voltage rating must be greater than input voltage. in nearly all cases a schottky diode is recommended. in low output voltage applications a low forward voltage provides improved efficiency. for high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. p-channel mosfet selection (q1) the important parameters for the pfet are the maximum drain-source voltage (v ds ), the on resistance (r dson ), current rating, and the input capacitance. the voltage across the pfet when it is turned off is equal to the sum of the input voltage and the diode forward voltage. the v ds must be selected to provide some margin beyond the input voltage. pfet drain current, id, must be rated higher than the peak inductor current, i ind-peak . depending on operating conditions, the pgate voltage may fall as low as v in - 8.3v. therefore, a pfet must be selected with a v gs maximum rating greater than the maximum pgate swing voltage. as input voltage decreases below 9v, pgate swing voltage may also decrease. at 5.0v input the pgate will swing from v in to v in - 4.6v. to ensure that the pfet turns on quickly and completely, a low threshold pfet should be used when the input voltage is less than 7v. total power loss in the fet can be approximated using the following equation: pd switch = r dson x i out 2 x d + f x i out x v in x (t on + t off )/2 (16) where: t on = fet turn on time t off = fet turn off time a value of 10ns to 20ns is typical for ton and toff. a pfet should be selected with a turn on rise time of less than 100ns. slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the pgate pin. the r dson is used in determining the current limit resistor value, r adj . note that the r dson has a positive temperature coefficient. at 100 c, the r dson may be as much as 150% higher than the 25 c value. this increase in r dson must be considered when determining r adj in wide temperature range applications. if the current limit is set based upon 25 c ratings, then false current limiting can occur at high temperature. keeping the gate capacitance below 2000pf is recommended to keep switching losses and transition times low. this will also help keep the pfet drive current low, which will improve efficiency and lower the power dissipation within the controller. as gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases operating frequency can be increased. interfacing with the enable pin the enable pin is internally pulled high with clamping at 8v typical. for normal operation this pin should be left open. to disable the device, the enable pin should be connected to ground externally. if an external voltage source is applied to this pin for enable control, the applied voltage should not exceed the maximum operating voltage level specified in this datasheet, i.e. 5.5v. for most applications, an open drain or open collector transistor can be used to short this pin to ground to shutdown the device . 16 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1
lm3489 lm3489-q1 www.ti.com snvs443b ? may 2006 ? revised february 2013 pcb layout the pcb board layout is very important in all switching regulator designs. poor layout can cause switching noise into the feedback signal and generate emi problems. for minimal inductance, the wires indicated by heavy lines in schematic diagram should be as wide and short as possible. keep the ground pin of the input capacitor as close as possible to the anode of the catch diode. this path carries a large ac current. the switching node, the node with the diode cathode, inductor and fet drain should be kept short. this node is one of the main sources for radiated emi since it sees a large ac voltage at the switching frequency. it is always a good practice to use a ground plane in the design, particularly for high current applications. the two ground pins, pgnd and gnd, should be connected by as short a trace as possible. they can be connected underneath the device. these pins are resistively connected internally by approximately 50 ? . the ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the fb divider and c out grounds. the gate pin of the external pfet should be located close to the pgate pin. however, if a very small fet is used, a resistor may be required between pgate pin and the gate of the pfet to reduce high frequency ringing. since this resistor will slow down the pfet ? s rise time, the current limit blanking time should be taken into consideration (refer to current limiting operation). the feedback voltage signal line can be sensitive to noise. avoid inductive coupling with the inductor or the switching node. the fb trace should be kept away from those areas. also, the orientation of the inductor can contribute un-wanted noise coupling to the fb path. if noise problems are observed it may be worth trying a different orientation of the inductor and select the best for final component placement. figure 30. typical application schematic for vout = 3.3v/500ma copyright ? 2006 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: lm3489 lm3489-q1 isense adj vin pgate fb en lm3489 gnd pgnd 7 2 3 4 5 6 1 8 + + q1 fdc5614p v in v out c in1 c out d1 l 22 p h r adj c adj r1 r2 c ff c in2 7v 35v 22 p f 50v 0.1 p f 50v 3.3v/0.5a 1 nf 24k 33k 20k 100 pf 100 p f 6.3v mbrs140 sd* * short to shutdown the device r is 270
lm3489 lm3489-q1 snvs443b ? may 2006 ? revised february 2013 www.ti.com revision history changes from revision a (february 2013) to revision b page ? changed layout of national data sheet to ti format .......................................................................................................... 17 18 submit documentation feedback copyright ? 2006 ? 2013, texas instruments incorporated product folder links: lm3489 lm3489-q1
package option addendum www.ti.com 22-sep-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm3489mm nrnd vssop dgk 8 1000 tbd call ti call ti -40 to 125 sksb lm3489mm/nopb active vssop dgk 8 1000 green (rohs & no sb/br) cu nipdauag | cu sn level-1-260c-unlim -40 to 125 sksb lm3489mmx/nopb active vssop dgk 8 3500 green (rohs & no sb/br) cu nipdauag | cu sn level-1-260c-unlim -40 to 125 sksb lm3489qmm/nopb active vssop dgk 8 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 steb lm3489qmmx/nopb active vssop dgk 8 3500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 steb (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 22-sep-2015 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lm3489, lm3489-q1 : ? catalog: lm3489 ? automotive: lm3489-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lm3489mm vssop dgk 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3489mm/nopb vssop dgk 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3489mm/nopb vssop dgk 8 1000 178.0 13.4 5.3 3.4 1.4 8.0 12.0 q1 lm3489mmx/nopb vssop dgk 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3489mmx/nopb vssop dgk 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3489qmm/nopb vssop dgk 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3489qmmx/nopb vssop dgk 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 package materials information www.ti.com 23-may-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lm3489mm vssop dgk 8 1000 210.0 185.0 35.0 lm3489mm/nopb vssop dgk 8 1000 210.0 185.0 35.0 lm3489mm/nopb vssop dgk 8 1000 202.0 201.0 28.0 lm3489mmx/nopb vssop dgk 8 3500 364.0 364.0 27.0 lm3489mmx/nopb vssop dgk 8 3500 367.0 367.0 35.0 lm3489qmm/nopb vssop dgk 8 1000 210.0 185.0 35.0 lm3489qmmx/nopb vssop dgk 8 3500 367.0 367.0 35.0 package materials information www.ti.com 23-may-2016 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated

▲Up To Search▲

Price & Availability of LM3489QMMNOPB

	To Download LM3489QMMNOPB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .